The fabrication process by which an integrated circuit device is formed is a complex process. The integrated circuit device is fabricated upon a wafer, the integrated circuit (IC) wafer, and subsequently packaged into an integrated circuit (IC) package.
Even when the fabrication process is closely controlled and maintained under strict supervision, defective integrated circuit wafers are sometimes formed. And, packaging errors, such as missed connections or misconnections, can occur during packaging of the integrated circuit device. Testing for defects and packaging errors is therefore required to ensure that a defective IC package is not used in an electronic circuit.
On-wafer testing, subsequent to fabrication of the IC wafer and prior to packaging of the integrated circuit device can detect defects on the integrated circuit device. Testing for packaging errors must necessarily be performed subsequent to packaging operations. Sometimes, on-wafer testing is partially or completely deferred, and testing occurs only after packaging. Such deferral is, however, at the cost, typically, of the resultant need to discard an increased number of packaged, integrated circuit devices. Defects which would otherwise be detected on-wafer are detected only after packaging of the integrated circuit devices.
With the trend towards evermore densely populated integrated circuit devices having more highly integrated components operable at higher frequencies of operation, the problems attendant to the testing of an integrated circuit wafer or a packaged integrated circuit device formed therefrom become more complex.
As the integrated circuits have become increasingly more highly-integrated, boundary scan techniques for detecting faults have become widely utilized. Standard methodologies of boundary scan testing have been set forth. For instance, the Institute of Electrical and Electronics Engineers (IEEE) standard test access port and boundary scan architecture, IEEE Standard 1149.1-1990, has been promulgated to set forth industry-wide standards for boundary scan testing.
In general, such standards call for the formation of a test access port (TAP) state machine which allows control and access to a boundary scan architecture. To implement the boundary scan architecture, the integrated circuit device must include the boundary scan cells which are implemented between component terminals and internal logic circuitry of the integrated circuit device. The boundary scan cells are also connected together to form a shift register path around the periphery of the integrated circuit device, thus giving rise to the term boundary scan.
Boundary scan techniques can also be utilized to test the integrated circuit device while still on-wafer. Testing of the internal logic of the integrated circuit device is possible by way of the test port. Boundary scan functions can be used for the testing of primary inputs and outputs of the integrated circuit device to achieve controllability and observability of the chip-interior side of the input and output terminals.
Conventionally, automatic test equipment (ATE) is utilized for testing of integrated circuit devices. Conventional ATE typically includes a "testhead" and a workstation to provide operator control of the integrated circuit device undergoing testing, the "device under test" (DUT). A fixture is required to interconnect, or interface, the testing equipment with the integrated circuit device. Such a fixture is of dimensional, and other, characteristics corresponding to the particular integrated circuit device. A probe card having pin contactors, or probe "needles", for connecting with terminals of the integrated circuit device connects the integrated circuit device with the test resources of the ATE. The ATE typically utilizes three kinds of test resources: drivers which drive logic inputs, comparators for interpreting output data, and programmable power supplies.
As the integrated circuit devices become increasingly integrated and have increasing numbers of input and output terminals, commensurate increase in the capacity of ATEs to test the integrated circuit devices, particularly at the high frequencies of operation of the integrated circuits is not practical. Further, differential terminals are oftentimes utilized in high-speed integrated circuit devices. Differential terminals are formed of terminal pairs in which differential signals are offset in voltage relative to one another, one signal referred to as the positive signal and the other signal referred to as the negative signal. An external positive differential of signals applied to a terminal pair corresponds to an internal logical "1", an external negative differential corresponds to an internal logical "0". To be able to measure correctly a differential signal in a non-idealized environment, differential receivers are required. Existing ATEs include merely voltage comparators capable of quantizing signals in three voltage windows relative to a ground potential and are additionally inadequate to test many integrated circuit devices for this reason.
Therefore, existing apparatus and methodologies of testing complex, integrated circuit devices are inadequate to test properly the integrated circuit devices. And, as the size, complexity, and operational frequencies of state-of-the-art, integrated circuit devices continue to increase, the need for improved manners by which to test the integrated circuit devices shall become even more pressing.
Testing apparatus which permits appropriate and economic testing of such integrated circuit devices, operable at high frequencies of operation, is therefore necessary.
It is in light of this background information related to testing apparatus for testing integrated circuits that the significant improvements of the present invention have evolved.